From f8036bacb8f3e9f18207e4bae87bafc89aedb1f2 Mon Sep 17 00:00:00 2001 From: "yu.dongliang" <18588496441@163.com> Date: Thu, 29 Jun 2023 22:06:49 +0800 Subject: [PATCH] fix: arm64 for code below, bit xor(bit x, bit y) { return (x | y) & ~(x & y); } --- core/scf_type_cast.c | 2 ++ native/risc/scf_arm64.c | 2 +- native/risc/scf_risc_inst.c | 16 ++++++++-------- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/core/scf_type_cast.c b/core/scf_type_cast.c index 520875e..e0e7bab 100644 --- a/core/scf_type_cast.c +++ b/core/scf_type_cast.c @@ -4,6 +4,7 @@ static int type_update[] = { SCF_VAR_I8, SCF_VAR_CHAR, + SCF_VAR_BIT, SCF_VAR_U8, SCF_VAR_I16, @@ -26,6 +27,7 @@ static int type_update[] = static scf_type_cast_t base_type_casts[] = { {"char", -1, SCF_VAR_CHAR, scf_cast_to_u8}, + {"bit", -1, SCF_VAR_BIT, scf_cast_to_u8}, {"u8", -1, SCF_VAR_U8, scf_cast_to_u8}, {"u16", -1, SCF_VAR_U16, scf_cast_to_u16}, {"u32", -1, SCF_VAR_U32, scf_cast_to_u32}, diff --git a/native/risc/scf_arm64.c b/native/risc/scf_arm64.c index a648800..618e909 100644 --- a/native/risc/scf_arm64.c +++ b/native/risc/scf_arm64.c @@ -877,7 +877,7 @@ scf_instruction_t* arm64_inst_MVN(scf_3ac_code_t* c, scf_register_t* rd, scf_reg scf_instruction_t* inst; uint32_t opcode; - opcode = (0xaa << 24) | (0x1 << 21) | (rs->id << 16) | (0x1f << 10) | rd->id; + opcode = (0xaa << 24) | (0x1 << 21) | (rs->id << 16) | (0x1f << 5) | rd->id; inst = risc_make_inst(c, opcode); return inst; diff --git a/native/risc/scf_risc_inst.c b/native/risc/scf_risc_inst.c index e5517c2..79459f6 100644 --- a/native/risc/scf_risc_inst.c +++ b/native/risc/scf_risc_inst.c @@ -617,7 +617,7 @@ static int _risc_inst_bit_not_handler(scf_native_t* ctx, scf_3ac_code_t* c) if (!c->srcs || c->srcs->size != 1) return -EINVAL; - scf_risc_context_t* risc = ctx->priv; + scf_risc_context_t* risc = ctx->priv; scf_function_t* f = risc->f; scf_3ac_operand_t* src = c->srcs->data[0]; scf_3ac_operand_t* dst = c->dsts->data[0]; @@ -634,9 +634,9 @@ static int _risc_inst_bit_not_handler(scf_native_t* ctx, scf_3ac_code_t* c) return -ENOMEM; } - scf_register_t* rd = NULL; - scf_register_t* rs = NULL; scf_instruction_t* inst = NULL; + scf_register_t* rd = NULL; + scf_register_t* rs = NULL; scf_dag_node_t* s = src->dag_node; scf_dag_node_t* d = dst->dag_node; @@ -2820,7 +2820,7 @@ static int _risc_inst_bit_and_handler(scf_native_t* ctx, scf_3ac_code_t* c) } RISC_SELECT_REG_CHECK(&rd, d, c, f, 0); - RISC_SELECT_REG_CHECK(&rn, d, c, f, 1); + RISC_SELECT_REG_CHECK(&rn, s0, c, f, 1); if (0 == s1->color) { @@ -2854,10 +2854,10 @@ static int _risc_inst_bit_or_handler(scf_native_t* ctx, scf_3ac_code_t* c) { RISC_INST_OP3_CHECK() - scf_register_t* rm = NULL; - scf_register_t* rn = NULL; - scf_register_t* rd = NULL; scf_instruction_t* inst = NULL; + scf_register_t* rm = NULL; + scf_register_t* rn = NULL; + scf_register_t* rd = NULL; scf_dag_node_t* d = dst ->dag_node; scf_dag_node_t* s0 = src0->dag_node; scf_dag_node_t* s1 = src1->dag_node; @@ -2884,7 +2884,7 @@ static int _risc_inst_bit_or_handler(scf_native_t* ctx, scf_3ac_code_t* c) } RISC_SELECT_REG_CHECK(&rd, d, c, f, 0); - RISC_SELECT_REG_CHECK(&rn, d, c, f, 1); + RISC_SELECT_REG_CHECK(&rn, s0, c, f, 1); if (0 == s1->color) { -- 2.25.1