add some simple GATE module combined with TTL Nand gate
authoryu.dongliang <18588496441@163.com>
Fri, 11 Apr 2025 12:07:22 +0000 (20:07 +0800)
committeryu.dongliang <18588496441@163.com>
Fri, 11 Apr 2025 12:07:22 +0000 (20:07 +0800)
commit8fa58608753d33812cb2b8100c17b8aea677503d
tree1bfeb0a466f07612682dd790f663fa001ab12011
parentc1d179606184c88e392e43e5c863b53cc6fdea43
add some simple GATE module combined with TTL Nand gate
35 files changed:
cpk/Makefile
cpk/ttl_add.cpk
cpk/ttl_and.cpk
cpk/ttl_and2_or.c [new file with mode: 0644]
cpk/ttl_and2_or.cpk [new file with mode: 0644]
cpk/ttl_and2_or_test.c [new file with mode: 0644]
cpk/ttl_if.c [new file with mode: 0644]
cpk/ttl_if.cpk [new file with mode: 0644]
cpk/ttl_if_test.c [new file with mode: 0644]
cpk/ttl_mla.c [new file with mode: 0644]
cpk/ttl_mla.cpk [new file with mode: 0644]
cpk/ttl_mla_test.c [new file with mode: 0644]
cpk/ttl_nand4.c [new file with mode: 0644]
cpk/ttl_nand4.cpk [new file with mode: 0644]
cpk/ttl_nand4_test.c [new file with mode: 0644]
cpk/ttl_nand_delay.c [deleted file]
cpk/ttl_nor.cpk
cpk/ttl_not.c [new file with mode: 0644]
cpk/ttl_not.cpk [new file with mode: 0644]
cpk/ttl_or.cpk
cpk/ttl_xor.cpk
main.c
scf_eda_pack.c
scf_eda_pack.h
ses_layout.c
ses_layout_function.c
ses_node_analysis.c
ses_step_dc_input.c
ses_step_draw.c
ses_step_open.c
ses_step_topo.c
ses_step_va.c
test/Makefile
test/fft.c
test/main.c