make a framework for RISC register selection
authoryu.dongliang <18588496441@163.com>
Wed, 3 May 2023 07:21:57 +0000 (15:21 +0800)
committeryu.dongliang <18588496441@163.com>
Wed, 3 May 2023 07:22:17 +0000 (15:22 +0800)
commit2b0c0991001bbf11f484da7ea2ad16af9d2303d0
treeef930b28f4a3364244e1957aba36ca97c86be9c2
parent015bda09784c7cfaefac83f9b9a1743308ba51f9
make a framework for RISC register selection
15 files changed:
core/scf_core_types.h
core/scf_function.h
native/risc/scf_arm64.c
native/risc/scf_naja.c
native/risc/scf_risc.c
native/risc/scf_risc.h
native/risc/scf_risc_bb_color.c
native/risc/scf_risc_inst.c
native/risc/scf_risc_rcg.c
native/risc/scf_risc_reg.c
native/risc/scf_risc_reg.h
native/risc/scf_risc_reg_arm64.c [new file with mode: 0644]
native/scf_native.h
parse/Makefile
vm/scf_vm.h